Architecture Analysis and Design of the Platform Based Wireless Communication Systems
2005년 제출했던 나의 박사논문
플랫폼 기반의 무선통신 시스템을 설계하기 위한 분석 및 설계과정에 대한 내용이다.
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ABSTRACT
In this dissertation, the super-iterative LDPC-coded MIMO-OFDM system is analyzed, designed and implemented as a target system. The receiver performance and the low-power designing techniques are summarized and applied. Based on the Monte-Carlo simulation results, the throughput of the target system is evaluated for different system parameters such as the modulation order, number of antennas, and receiver configurations. The receiver configurations including the MIMO detection scheme, LDPC decoding scheme, and number of iterations are analyzed. The simulation results show that the throughput can be enhanced when the modulation order grows with a SNR at the receiver side and a larger number of antennas are utilized. Furthermore, it is found that using iterative detection and decoding with sufficiently large number of iterations, more than 4 iterations, increase the throughput.
The extracted parameters by system simulation are applied to actual hardware design. Moreover, the low-power digital hardware design techniques, such as clock gating, operand isolation, and low-power cell replacement, are analyzed and applied to the designed system. By these techniques, total power reduction of 80 % is achieved.
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Contents
2. Platform Based Wireless SoC Design
2.2 Characteristics of Wireless SoC System
2.2.3 Critical Requirements for Latency and Throughput
2.3 Latency-Throughput Computation
2.3.2 For Multi-Processor using Simple Protocol
2.3.3 For Multi-Processor using Synchronous Protocol
2.5 Example of Derivative System
2.5.3 For Multi-Processor using Simple Protocol
2.5.4 For Multi-Processor using Synchronous Protocol
3. Overview of the MIMO-WLAN Systems
3.2 Promising Proposals for the MIMO-WLAN Systems
3.2.2 WWiSE (World-Wide Spectrum Efficiency)
3.3 MIMO Schemes for the MIMO-WLAN System
3.3.2 Closed-loop MIMO Schemes
4. Super iterative Decoding between MIMO detector and Channel Decoder
4.3 Iterative Demodulation and Decoding Structure
4.4 System Simulation Results of Coded MIMO-OFDM
5. Hardware Block Design of LDPC Coded MIMO-OFDM
5.3 Hardware Components Design
5.4 Adapting Hardware Optimizing Techniques
5.5 Implementation on Platform Board
6. Trade-offs of Performance and Cost
6.2 Hardware Resource Estimation
6.3 Trade-offs of Throughput and Hardware Resource and Power
7. Low Power Design for SoC Digital Design
7.2 Techniques for the power constraints
7.2.3 Low-power cell replacement
7.3 Power Modeling and Calculation
7.3.1 Static and dynamic power dissipations
7.4 Applying Low-Power Techniques
7.4.1 Low power design for LSD-MIMO block
7.4.2 Summary of adapting low power technique
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